Shared write buffer for use by multiple processor units
作者： Marc Tremblay , Anup S. Tirumala , Andre Kowalczyk
DOI:
关键词:
摘要: A shared write back buffer for storing data from a cache to be written memory. The includes plurality of ports, each port being associated with one processing units. All units in the share buffer. further register provided through input an address addresses and single output providing
google.co.uk 参考文章(14)
Gene F. Young, Roy M. Stevens, Larry C. James, Directory-based coherency system for maintaining coherency in a dual-ported memory system ,(1996)
Linda L. Santoline, William D. Ghrist, Charles J. Roslund, Gilbert W. Remley, Albert W. Crew, Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory ,(1989)
A. Miyoshi, H. Okuyama, S. Ozaki, T. Tsuki, K. Kaneko, S. Ogura, Y. Nishimichi, A write-back cache memory using bit-line steal technique 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215). pp. 180- 181 ,(1998) , 10.1109/VLSIC.1998.688076
Marc A. Quattromani, Raul A. Garibay, Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch ,(1995)
Michael T. Jackson, Walter G. Fry, Alan L. Goodrum, Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system ,(1994)
Timothy J. Heeter, Adriano Roganti, Roger A. Smith, John D. Acton, Paardeep K. Sood, Method and apparatus for sharing information between a plurality of processing units ,(1991)
Marc Tremblay, Anup S. Tirumala, Multiple variable cache replacement policy ,(2001)
Maurice Herlihy, J. Eliot B. Moss, System for achieving atomic non-sequential multi-word operations in shared memory ,(1992)
T. Stricker, T. Gross, Optimizing memory system performance for communication in parallel computers international symposium on computer architecture. ,vol. 23, pp. 308- 319 ,(1995) , 10.1145/223982.224442
Yet-Ping Pai, Le T. Nguyen, Cache control unit with a cache request transaction-oriented protocol ,(1996)