Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization

作者: Angelo G da Luz , Eduardo AC da Costa , Marilton S de Aguiar , None

DOI: 10.1145/2020876.2020898

关键词:

摘要: This paper proposes the exploration of different heuristic-based algorithms for best ordering and partitioning coefficients in Finite Impulse Response (FIR) filters. Due to characteristics FIR filter algorithms, which involve multiplications input data with appropriate coefficients, these operations can contribute reduction switching activity, what leads minimization power consumption Two named Nearest neighbor Bellmore Nemhauser are used tests. A new algorithm Anedma is proposed get as near possible optimal solution larger instances. set were tests, results presented terms Hamming distance between consecutive coefficients. Sequential semi-parallel architectures implemented ordered partitioned. As will be shown, depending on used, based guidance given by heuristic reduced significantly.

参考文章(11)
E. da Costa, P. Flores, J. Monteiro, Maximal sharing of partial terms in MCM under minimal signed digit representation european conference on circuit theory and design. ,vol. 2, pp. 221- 224 ,(2005) , 10.1109/ECCTD.2005.1523033
Eduardo AC da Costa, José C Monteiro, Sergio Bampi, None, Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths VLSI-SOC. pp. 281- 297 ,(2006) , 10.1007/0-387-33403-3_18
Mahesh Mehendale, S. D. Sherlekar, G. Venkatesh, Techniques for low power realization for FIR filters Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95. pp. 72- ,(1995) , 10.1145/224818.224952
Angelo G da Luz, Eduardo AC da Costa, Marilton S de Aguiar, None, Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization symposium on integrated circuits and systems design. pp. 180- 185 ,(2010) , 10.1145/1854153.1854198
Edwin Hou, Nirwan Ansari, Computational intelligence for optimization ,(1996)
E. Costa, S. Bampi, J. Monteiro, A new architecture for signed radix-2/sup m/ pure array multipliers international conference on computer design. pp. 112- 117 ,(2002) , 10.1109/ICCD.2002.1106756
Leandro Zafalon Pieper, Eduardo Costa, Sérgio J. M. de Almeida, Sergio Bampi, José C. Monteiro, Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-2m Array Multipliers Journal of Computers. ,vol. 5, pp. 1502- 1509 ,(2010) , 10.4304/JCP.5.10.1502-1509
H. Mehendale, S.D. Sherlekar, G. Venkatesh, Algorithmic and architectural transformations for low power realization of FIR filters international conference on vlsi design. pp. 12- 17 ,(1998) , 10.1109/ICVD.1998.646571
M. Mehendale, S.D. Sherlekar, G. Venkatesh, Low-power realization of FIR filters on programmable DSPs IEEE Transactions on Very Large Scale Integration Systems. ,vol. 6, pp. 546- 553 ,(1998) , 10.1109/92.736126