作者: Sidinei Ghissoni , Eduardo AC da Costa , Angelo Gonçalves da Luz , None
DOI: 10.1109/VLSI-SOC.2014.7004162
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摘要: This paper addresses the reordering of coefficients, i.e., twiddle factors in multicore FFT order to obtain power efficient datapaths. The coefficients are divided smaller ones into different cores and they reordered through Improved Anedma heuristic-based algorithm. According characteristics algorithms, which involve multiplications input data with appropriate best ordering these operations, each core, can contribute for reduction switching activity, what leads minimization consumption FFTs. Therefore, allows finding architecture terms both performance consumption. architectures were synthesized using SYNOPSYS Design Compiler XFAB 180 nm technology. results show that it is possible achieve FFTs close 9%, on average, after cores.