Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

作者: L. Shifren , X. Wang , P. Matagne , B. Obradovic , C. Auth

DOI: 10.1063/1.1841452

关键词:

摘要: Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress achieve performance gain in both n-type MOSFETs (NMOS) and p-type (PMOS). The physics behind NMOS is better understood than of PMOS gain, which received less attention. In this letter, we describe the warping phenomena responsible for seen [110] uniaxially stressed devices on [100] orientated wafers. We also demonstrate shear uniaxial suited MOSFET applications biaxial as it able maintain at high vertical lateral fields.

参考文章(9)
J.L. Hoyt, H.M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E.A. Fitzgerald, D.A. Antoniadis, Strained silicon MOSFET technology international electron devices meeting. pp. 23- 26 ,(2002) , 10.1109/IEDM.2002.1175770
G.F Formicone, D Vasileska, D.K Ferry, Transport in the surface channel of strained Si on a relaxed Si1−xGex substrate Solid-state Electronics. ,vol. 41, pp. 879- 885 ,(1997) , 10.1016/S0038-1101(97)00042-7
Martin M. Rieger, P. Vogl, Electronic-band parameters in strained Si 1 − x Ge x alloys on Si 1 − y Ge y substrates Physical Review B. ,vol. 48, pp. 14276- 14287 ,(1993) , 10.1103/PHYSREVB.48.14276
MV Fischetti, F Gamiz, W Hänsch, On the enhanced electron mobility in strained-silicon inversion layers Journal of Applied Physics. ,vol. 92, pp. 7320- 7324 ,(2002) , 10.1063/1.1521796
A. Duncan, U. Ravaioli, J. Jakumeit, Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors IEEE Transactions on Electron Devices. ,vol. 45, pp. 867- 876 ,(1998) , 10.1109/16.662792
N. Sugii, D. Hisamoto, K. Washio, N. Yokoyama, S. Kimura, Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate IEEE Transactions on Electron Devices. ,vol. 49, pp. 2237- 2243 ,(2002) , 10.1109/TED.2002.805231
S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, Y. El-Mansy, A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters. ,vol. 25, pp. 191- 193 ,(2004) , 10.1109/LED.2004.825195
K. Rim, J.L. Hoyt, J.F. Gibbons, Fabrication and analysis of deep submicron strained-Si n-MOSFET's IEEE Transactions on Electron Devices. ,vol. 47, pp. 1406- 1415 ,(2000) , 10.1109/16.848284
S. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, M. Bohr, A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell international electron devices meeting. pp. 61- 64 ,(2002) , 10.1109/IEDM.2002.1175779