A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC
作者： Indrit Myderrizi , Ali Zeki
DOI: 10.1007/S10470-009-9448-X
关键词:
摘要: In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of offer advantages like speed up, easiness in small active area. proposed consists four 3-bit parallel matched subDACs resistive networks that properly weight current output each subDAC to obtain overall voltage-mode DAC. performance validated through static dynamic metrics. Simulations indicate has an accuracy SFDR higher than 66 dB whole Nyquist frequency band. simulated INL better 1 LSB, while DNL 0.25 LSB. At update rate 250 MS/s signals up 10 MHz dB. Figure Merit (FoM) recently presented DACs with resolutions various technologies. supporting high rates good can be as alternative applications industry including video, digital TV, cable modems etc.
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