An implementation of a new 11-bit 1.2 GS/s hybrid DAC with a noval 3-bit Sub-DAC
作者： Hossein Ghasemian , Amirhossein Ahmadi , Ebrahim Abiri , Mohammad Reza Salehi
DOI: 10.1016/J.MEJO.2020.104872
关键词: Electronic engineering 、 Binary number 、 Spurious-free dynamic range 、 Resistor ladder 、 Power (physics) 、 Least significant bit 、 Voltage 、 Digital-to-analog converter 、 CMOS 、 Computer science
摘要: Abstract this brief presents a new 11-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology. In structure, combination of resistor ladder and current sources is used realize the DAC structure. The are connected different nodes logical way. situation, equal make voltage values. Furthermore, complicated binary thermometer decoders exchanged with basic logics. This technique remarkably reduces number needed for realization an leads circuit dissipates just 4.68 mW power while supply 1.2 V. Also, occupied area 0.0061 mm2. Post layout simulation results indicate that spurious-free dynamic range (SFDR) more than 70 dB over 600 MHz Nyquist BW. INL DNL parameters also obtained better 1.2 LSB 1 LSB, respectively.
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