A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM

摘要: A new segmented architecture is presented to improve the dynamic and static performance of current steering digital-to-analog converters (DACs). In proposed instead a single binary DAC, distributed cells are used. So effect mismatch timing errors not accumulated averaged out. For realization MSB unit those reused form larger weighted cells. Realization with smaller results in improved performances as effects gradient minimized nonlinear parasitic capacitances reduced. The DAC has been designed 180 nm five-metal nwell CMOS process. simulation show that can achieve maximum spurious free range (SFDR) 70.99 dB at 2.93 MHz signal for sampling rate 1 GSPS considering effects. simulated Nyquist SFDR >70 mismatch. third order intermodulation distortion (IM3) 71.40 dB, dual tone test 491.21 495.12 signals. optimized digital synthesis applications wireless base stations other communication applications. power dissipation 78.21 mW 498.05 1.8 V supply.