A 12-bit high performance current-steering DAC using a new binary to thermometer decoder
作者： Masoud Nazari , Leila Sharifi , Armin Aghajani , Omid Hashemipour
DOI: 10.1109/IRANIANCEE.2016.7585835
关键词:
摘要: A 12-bit 8-4 segmented current-steering digital to analog converter (DAC) is presented in this paper. The designed DAC consumes low power compared similar designs. number of control signals and chip area are also decreased considerably. High performance the proposed owes appropriate segmentation input bits employment a new nested Binary Thermometer (BT) decoder which uses domino logic gates. deployed 3 stages with repetitive gates pipelining scheme. Therefore, total dissipation 0.18 μm CMOS technology at sample rate 1 GHz approximately 62 mWatt. supply voltage 1.2 V while 1.8 V. In addition, over output bandwidth 500 MHz 1GS/s, spurious-free dynamic range (SFDR) reaches 60.8 dB.
sci-hub.se 参考文章(19)
Anne van den Bosch, Michiel Steyaert, Willy Sansen, An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters Analog Integrated Circuits and Signal Processing. ,vol. 29, pp. 173- 180 ,(2001) , 10.1023/A:1011261330190
D. Giotta, P. Pessl, M. Clara, W. Klatzer, R. Gaggl, Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS european solid-state circuits conference. pp. 163- 166 ,(2004) , 10.1109/ESSCIR.2004.1356643
Masoud Nazari, Armin Aghajani, Omid Hashemipour, Design of a new split-capacitive-array DAC based on distribution of attenuation capacitor iranian conference on electrical engineering. pp. 1370- 1373 ,(2015) , 10.1109/IRANIANCEE.2015.7146431
David Johns, Kenneth W. Martin, Tony Chan Carusone, Analog Integrated Circuit Design ,(1996)
Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio di Giandomenico, Luca Gori, A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS international solid-state circuits conference. pp. 250- 600 ,(2007) , 10.1109/ISSCC.2007.373388
Chi-Hung Lin, K. Bult, A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/ IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 1948- 1958 ,(1998) , 10.1109/4.735535
Santanu Sarkar, Swapna Banerjee, A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM Analog Integrated Circuits and Signal Processing. ,vol. 80, pp. 59- 68 ,(2014) , 10.1007/S10470-014-0309-X
Shu-Chung Yi, A 10-bit current-steering CMOS digital to analog converter Aeu-international Journal of Electronics and Communications. ,vol. 69, pp. 14- 17 ,(2015) , 10.1016/J.AEUE.2014.07.010
Peiman Aliparast, Ziaadin Daei Koozehkanany, Jafar Sobhi, Design of a 12-bit high-speed CMOS D/A converter using a new 3D digital decoder structure useful for wireless transmitter applications Analog Integrated Circuits and Signal Processing. ,vol. 68, pp. 315- 328 ,(2011) , 10.1007/S10470-011-9647-0
Fang-Ting Chou, Chia-Min Chen, Chung-Chih Hung, A low-glitch binary-weighted DAC with delay compensation scheme Analog Integrated Circuits and Signal Processing. ,vol. 79, pp. 277- 289 ,(2014) , 10.1007/S10470-014-0262-8