A 12-bit intrinsic accuracy high-speed CMOS DAC

作者: J. Bastos , A.M. Marques , M.S.J. Steyaert , W. Sansen

DOI: 10.1109/4.735536

关键词:

摘要: … averaging) current-steering segmented architecture DAC implemented in a standard twin-… of the DAC design are discussed in the next sections. In Section II an overview of the DAC …

参考文章(22)
P. Hendriks, Specifying communications DACs IEEE Spectrum. ,vol. 34, pp. 58- 69 ,(1997) , 10.1109/MSPEC.1997.609817
H.J. Schouwenaars, D.W.J. Groeneveld, H.A.H. Termeer, A low-power stereo 16-bit CMOS D/A converter for digital audio IEEE Journal of Solid-state Circuits. ,vol. 23, pp. 1290- 1297 ,(1988) , 10.1109/4.90024
M.J.M. Pelgrom, A 10-b 50-MHz CMOS D/A converter with 75- Omega buffer IEEE Journal of Solid-state Circuits. ,vol. 25, pp. 1347- 1352 ,(1990) , 10.1109/4.62178
T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, Y. Horiba, An 80-MHz 8-bit CMOS D/A converter IEEE Journal of Solid-state Circuits. ,vol. 21, pp. 983- 988 ,(1986) , 10.1109/JSSC.1986.1052639
M. Pelgrom, A 50 MHz 10-bit CMOS digital-to-analog converter with 75 Omega buffer international solid-state circuits conference. pp. 200- 201 ,(1990) , 10.1109/ISSCC.1990.110194
H. Kohno, Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, K. Okada, A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme custom integrated circuits conference. pp. 211- 214 ,(1995) , 10.1109/CICC.1995.518170
J. Bastos, M. Steyaert, W. Sansen, A high yield 12-bit 250-MS/s CMOS D/A converter custom integrated circuits conference. pp. 431- 434 ,(1996) , 10.1109/CICC.1996.510591
Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, N. Yazawa, A 10-b 70-MS/s CMOS D/A converter IEEE Journal of Solid-state Circuits. ,vol. 26, pp. 637- 642 ,(1991) , 10.1109/4.75066
K.R. Lakshmikumar, R.A. Hadaway, M.A. Copeland, Characterisation and modeling of mismatch in MOS transistors for precision analog design IEEE Journal of Solid-state Circuits. ,vol. 21, pp. 1057- 1066 ,(1986) , 10.1109/JSSC.1986.1052648
D. Mercer, A 16-b D/A converter with increased spurious free dynamic range IEEE Journal of Solid-state Circuits. ,vol. 29, pp. 1180- 1185 ,(1994) , 10.1109/4.315200