作者: Vishwani D. Agrawal , Sharad C. Seth , Prathima Agrawal
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摘要: At present, the relationship between fault coverage of LSI circuit tests and tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a that too high (99 percent or higher). This difficult to achieve circuits. paper proposes model distribution chip. The number faults defective chip assumed have Poisson density which average value determined through experiment actual chips. procedure, relates being studied, simple; one more fabricated lots must be by few preliminary test patterns. Once characterized, required can easily any given rate. main advantage such it adapts itself various characteristics (technology, feature size, manufacturing environment, etc.) (e.g., stuck-type faults). As example, technique was applied circuit; realistic results were obtained.