Bachus: A VLSI Architecture for a Large Binary Associative Memory

摘要: In recent years many attempts have been made to realise neural networks using VLSI technology. Thereby, major difficulties are how implement several hundreds or, if possible, thousands of highly interconnected neurons with their synapses on the area one chip or develop cascadeable architectures. Due large number conceivable architectures many, more less convincing approaches made. Some them trying take advantage analog circuits, whereby has into account problems concerning parameters depending fabrication and temperature. Other researchers developed wholly digital causing area, synchronisation, information exchange in networks. With this paper we want present a implementation binary network lack on-chip learning support use industrial standard RAMs, able offer an extremely dense storage synaptic weights. Therefore, it is feasible structures thousand completely connected neurons. Such may be used for applications areas speech image recognition.