作者: Zhenjie Tang , Rong Li , Dan Hu , Xiwei Zhang , Yage Zhao
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摘要: The postdeposition annealing (PDA)-treated charge-trap flash memory capacitor with stacked Zr0.46Si0.54O2/Al2O3 charge-trapping layer flanked by a SiO2 tunneling oxide and an Al2O3 blocking was fabricated investigated. It is observed that the exhibits prominent characteristics large windows 12.8 V in ±10 V gate sweeping voltage range, faster program/erase speed, good data-retention even at 125 °C compared to single (Zr0.46Si0.54O2, Zr0.79Si0.21O2, Zr0.46Al1.08O2.54). quantum wells introduced interfacial traps of trapping regulate storage loss behavior charges, jointly contribute improved characteristics. Hence, promising candidate future nonvolatile device design application.