PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

作者: Larry McMurchie , Carl Ebeling

DOI: 10.1145/201310.201328

关键词:

摘要: Routing FPGAs is a challenging problem because of the relative scarcity routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or failure route all signals. paper presents PathFinder, router balances goals performance routability. PathFinder uses an iterative algorithm converges solution in which signals are routed while achieving close optimal allowed placement. Routability achieved forcing negotiate for resource thereby determine signal needs most. Delay minimized allowing more critical greater say this negotiation. Because requires only directed graph describe architecture it adapts readily wide variety FPGA architectures such as Triptych, Xilinx 3000 mesh-connected arrays FPGAs. The results ISCAS benchmarks on Triptych show average increase 4.5% path delay over optimum Routes completion rate than commercial tools, well 11% faster implementations.

参考文章(18)
Gaetano Borriello, Scott Hauck, Carl Ebeling, TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing ,(1992)
Darren C. Cronquist, Larry McMurchie, Emerald - An Architecture-Driven Tool Compiler for FPGAs field programmable gate arrays. ,vol. 1, pp. 144- 150 ,(1996) , 10.1145/228370.228391
Peter Hart, Nils Nilsson, Bertram Raphael, A Formal Basis for the Heuristic Determination of Minimum Cost Paths IEEE Transactions on Systems Science and Cybernetics. ,vol. 4, pp. 100- 107 ,(1968) , 10.1109/TSSC.1968.300136
Ralph Linsker, An iterative-improvement penalty-function-driven wire routing system Ibm Journal of Research and Development. ,vol. 28, pp. 613- 624 ,(1984) , 10.1147/RD.285.0613
James P. Cohoon, Gabriel Robins, Michael J. Alexander, Joseph L. Ganley, An architecture-independent approach to FPGA routing based on multi-weighted graphs european design automation conference. pp. 259- 264 ,(1994) , 10.5555/198174.198256
R. Nair, A Simple Yet Effective Technique for Global Wiring IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 6, pp. 165- 172 ,(1987) , 10.1109/TCAD.1987.1270260
William A. Dees, Robert J. Smith, Performance of Interconnection Rip-Up and Reroute Strategies design automation conference. pp. 382- 390 ,(1981) , 10.5555/800073.802333
S. Brown, J. Rose, Z.G. Vranesic, A detailed router for field-programmable gate arrays international conference on computer aided design. ,vol. 11, pp. 620- 628 ,(1990) , 10.1109/43.127623
M. Palczewski, Plane parallel a maze router and its application to FPGAs design automation conference. pp. 691- 697 ,(1992) , 10.5555/113938.149679