Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach

摘要: Recently in cryptography and security, the multipliers with subquadratic space complexity for trinomials some specific pentanomials have been proposed. For such kind of multipliers, alternatively, we use double basis multiplication which combines polynomial modified to develop a new efficient digit-serial systolic multiplier. The proposed multiplier depends on almost equally (AESPs), utilizes Toeplitz matrix-vector product scheme derive low-latency architecture. If selected digit-size is $d$ bits, both polynomials, i.e., AESPs, requires latency $2\left\lceil \!{\sqrt {{m \over d}}} \right\rceil\! $ , while traditional ones take at least $O\left({\left\lceil d}} \right\rceil} \right)$ clock cycles. Analytical application-specific integrated circuit (ASIC) synthesis results indicate that area time \times complexities our architecture are significantly lower than existing multipliers.