Semiconductor substrate structure for use in power ic device
作者： Akio Nakagawa , Tsuneo Ogura
DOI:
关键词:
摘要: A wafer substrate structure has a P type epitaxial layer. An N+ region separation layer is formed on the to define first closed and second neighboring thereto. Formed in are P- an N- stacked thereon serving as high-resistance for forming element. exists of These layers defined by separating single semiconductor diffused Forming high-voltage transistor power element be PN junction-separated brings "double junction separation" wherein electrically separated from also region.
lens.org 参考文章(9)
W. Knauer, Mechanism of the Penning Discharge at Low Pressures Journal of Applied Physics. ,vol. 33, pp. 2093- 2099 ,(1962) , 10.1063/1.1728902
T. Okabe, M. Kimura, I. Shimizu, Y. Nagai, M. Nagata, 180V analog-compatible, high-speed logic utilizing semi-well isolation technology international electron devices meeting. ,vol. 30, pp. 698- 701 ,(1984) , 10.1109/IEDM.1984.190819
J. Helmer, R. Jepsen, Electrical Characteristics of a Penning Discharge Proceedings of the IRE. ,vol. 49, pp. 1920- 1925 ,(1961) , 10.1109/JRPROC.1961.287721
Marco Siligoni, Flavio Villa, Vertical isolated-collector transistor of the pnp type incorporating a device for suppressing the effects of parasitic junction components ,(1989)
Yosuke Takagi, Yu Ohata, Tsuyoshi Kuramoto, Koichi Kitahara, Semiconductor device with isolation between MOSFET and control circuit ,(1988)
Franco Dr Bertotti, Salvatore Dr Musumeci, Giuseppe Ferla, Salvatore Raciti, Monolithically integrated semiconductor power device ,(1985)
Bernard W. Boland, Means and method for improved junction isolation ,(1984)
P. Rossel, M.O.S. technologies for smart power and high-voltage circuits Onde électrique. ,vol. 67, pp. 58- 69 ,(1987)
Mastromatteo Ubaldo, Bipolar integrated circuits ,(1986)