作者: Xuejun Liang , J.S.-N. Jean
DOI: 10.1109/TVLSI.2003.812306
关键词:
摘要: Image processing algorithms for template matching, two-dimensional (2-D) digital filtering, morphologic operations, and motion estimation share some common properties. They can all benefit from using reconfigurable computers that use coprocessor boards based on field-programmable gate array (FPGA) chips. This paper characterizes those applications as generalized matching (GTM) operations describes the mapping of GTM onto computers. A three-step approach is described. The first two steps enumerate prune design space basic building blocks, which consist FPGA buffers computation cores. last step to achieve a solution through an optimal combination these blocks where cost function time constraints are board resources. Various presented so introduce options blocks. Algorithms used Experimental results summarized reveal relationship between resource parameters.