Memory Access Optimization and RAM Inference for Pipeline Vectorization

摘要: This paper describes memory access optimization in the context of pipeline vectorization, a method for synthesizing hardware pipe- lines reconfigurable systems from software program loops. Since many algorithms coprocessors are I/O bound, throughput coprocessor is determined by external accesses. Thus optimizations directly improve system’s performance. Two kinds have been studied. First, we consider methods reducing number accesses based on saving frequently-used data on-chip storage. In particular, recent FPGAs provide RAM which can be used this purpose. We present inference, technique automatically extracts small RAMs to reduce Second, aim minimize time spent scheduling as parallel possible. only applies architectures with multiple banks. allocates arrays banks, thereby minimizing overall time.