Garp: a MIPS processor with a reconfigurable coprocessor

作者: J.R. Hauser , J. Wawrzynek

DOI: 10.1109/FPGA.1997.624600

关键词:

摘要: Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a …

参考文章(13)
Andre Maurice Dehon, Thomas Knight, Reconfigurable Architectures for General-Purpose Computing Massachusetts Institute of Technology. ,(1996)
M. Gokhale, W. Holmes, A. Kopser, S. Lucas, R. Minnich, D. Sweely, D. Lopresti, Building and using a highly parallel programmable logic array IEEE Computer. ,vol. 24, pp. 81- 89 ,(1991) , 10.1109/2.67197
P.M. Athanas, H.F. Silverman, Processor reconfiguration through instruction-set metamorphosis IEEE Computer. ,vol. 26, pp. 11- 18 ,(1993) , 10.1109/2.204677
E. Lemoine, D. Merceron, Run time reconfiguration of FPGA for scanning genomic databases field-programmable custom computing machines. pp. 90- 98 ,(1995) , 10.1109/FPGA.1995.477414
Rahul Razdan, Michael D. Smith, A high-performance microarchitecture with hardware-programmable functional units international symposium on microarchitecture. pp. 172- 180 ,(1994) , 10.1145/192724.192749
J.E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H.H. Touati, P. Boucard, Programmable active memories: reconfigurable systems come of age IEEE Transactions on Very Large Scale Integration Systems. ,vol. 4, pp. 611- 624 ,(1996) , 10.1109/92.486081
Gunther, Milne, Narasimhan, Assessing document relevance with run-time reconfigurable machines field-programmable custom computing machines. pp. 10- 17 ,(1996) , 10.1109/FPGA.1996.564737
A. DeHon, DPGA-coupled microprocessors: commodity ICs for the early 21st Century field programmable gate arrays. pp. 31- 39 ,(1994) , 10.1109/FPGA.1994.315596
Wittig, Chow, OneChip: an FPGA processor with reconfigurable logic 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines. pp. 126- 135 ,(1996) , 10.1109/FPGA.1996.564773