Performance Comparison of DAC’s using 45 nm Technology

作者: Sowjanya , Sunitha Lasrado

DOI: 10.1109/ICECA.2019.8821921

关键词:

摘要: In signal processing systems, Analog-to-Digital Converter (ADC) is one of the important component. It converts analog to digital. Depending on type ADC, blocks involved in design an ADC will vary. many applications power consumption and speed major component that effects performance device. One limiting block Digital-to-Analog (DAC). This paper gives insight DAC which be used different types ADC’s. The implementation are carried out with 45 nm technology Cadence Virtuoso tool consumed dissipation, propagation delay, Differential Non-Linearity (DNL), Integral (INL) Signal Noise Ratio (SNR) estimated.

参考文章(9)
Jayshri D. Dhande, Nikhil Bobade, Mahendra A. Gaikwad, Design of Successive Approximation Analog to Digital Converter with modified DAC International journal of engineering research and technology. ,vol. 3, ,(2014)
Masoud Nazari, Armin Aghajani, Omid Hashemipour, Design of a new split-capacitive-array DAC based on distribution of attenuation capacitor iranian conference on electrical engineering. pp. 1370- 1373 ,(2015) , 10.1109/IRANIANCEE.2015.7146431
Iffa Binti Sharuddin, L. Lee, An ultra-low power and area efficient 10 bit digital to analog converter architecture ieee international conference on semiconductor electronics. pp. 305- 308 ,(2014) , 10.1109/SMELEC.2014.6920858
Babita Diana K, D. Jackuline Moni, An ultra low power 8 bit SAR ADC suitable for wireless medical applications international conference on communication and signal processing. pp. 1969- 1973 ,(2014) , 10.1109/ICCSP.2014.6950188
Jung Heum Kim, Sang Heon Lee, Jae Hyeon Seong, Kwang Sub Yoon, Design of a 10-bit SAR ADC with enhancement of matching property on C-DAC array international soc design conference. pp. 239- 240 ,(2015) , 10.1109/ISOCC.2015.7401736
Arpit Kumar Baranwal, Anurag, Balwinder Singh, Design and analysis of 8 bit fully segmented digital to analog converter international conference on recent advances in engineering computational sciences. pp. 1- 4 ,(2015) , 10.1109/RAECS.2015.7453307
Sunil S. Parmar, Anuradha P. Gharge, R-2R ladder circuit design for 32-bit digital-to-analog converter (DAC) with noise analysis and performance parameters international conference on communication and signal processing. ,vol. 2016, pp. 0467- 0471 ,(2016) , 10.1109/ICCSP.2016.7754180
.M Savitha, R. Venkat Siva Reddy, 14 -bit Low Power Successive Approximation ADC using Two Step Split Capacitive array DAC with multiplexer switching. international conference on advances in electronics computers and communications. ,(2018) , 10.1109/ICAECC.2018.8479477
Shinwoong Park, Sanjay Raman, Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing IEEE Transactions on Very Large Scale Integration Systems. ,vol. 27, pp. 679- 690 ,(2019) , 10.1109/TVLSI.2018.2888593