QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations

摘要: Dual-Rail Precharge Logic (DPL) has proven to be an effective countermeasure logic style against Differential Power Analysis (DPA). All previous DPL architectures employ the precharge mechanism achieve DPA resistance. However, due its additional phase, inherent drawback of these lies within degraded performance (less than 1/2 times compared nominal data rate), and hence they are not suitable for applications where high is required. In this paper, we present Quadruple-Rail (QRL), a new DPA-hardened approach cryptographic implementations in FPGA. The main merit proposal that system throughput can effectively maintained by removing phase. By introducing synchronized identical quadruple-rail network, strengthened resistance achieved. order test robustness QRL DPA, launch on QRL-based standard AES processor Xilinx Virtex-5 experimental results show failed analyzing 100,000 power consumption traces, which achieves competitive level as typical schemes, gains at least 110 stronger unprotected AES.