Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics.

摘要: This paper reports on the direct qualitative and quantitative performance comparisons of field-effect transistors (FETs) based vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1-100) diameters 220-640 nm) fabricated same wafer substrate to prove feasibility employing 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) wet chemical is applied in realization vertically aligned GaN NWs metalorganic vapor-phase epitaxy (MOVPE)-based thin films specific doping profiles. The FETs are involving a stack n-p-n layers embedded inverted p-channel, top drain bridging contact, wrap-around gating technology. From electrical characterization integrated NWs, threshold voltage (Vth) (6.6 ± 0.3) V obtained, which sufficient safely operating these devices an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) used as gate dielectric material resulting nearly-zero hysteresis forward backward sweep Vth shift (ΔVth) ~0.2 V). Regardless required device processing optimization having better linearity profile, upscaling capability from single array terms produced currents could already be demonstrated. Thus, presented expected bridge nanoworld into macroscopic world, subsequently paves way innovative large-scale nanoelectronics.