High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing

摘要: Signal area efficiency in integrated circuit designs is improved by increasing the information of signal wiring on an circuit. Candidate signals are selected for combination prioritizing according to length travel, travel path, and content. Signals with low content greater distance between endpoints make poor utilization fixed provide best candidates improvement. which similar (substantially parallel) paths from point across combined improve chip efficiency. A variety techniques described combining low-information-content onto a small number wires, transmitting them over re-expanding at their destination. Assuming that combining/expanding circuitry occupies less space than point-to-point would otherwise be required, there net reduction area. One aspect invention directed using auto-routing switching signals. Another applying these design process.