作者: Charles H Dennison , Aftab Ahmad
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摘要: A method of forming a bit line over capacitor array memory cells includes, a) providing an word lines; b) active areas about the lines to define cell FETs; c) layer electrically insulating material and areas; d) first second respective contact openings through regions; e) conductive within which connects with regions, collectively extending elevationally above upper surface, connecting surface; f) in single step, chemical-mechanical polishing collective surface downwardly at least material, step effectively isolating from openings.