Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
作者： Daniel Fu , Carl G. Amdahl , Yuanlong Wang , Earl T. Cohen , Brian R. Biard
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摘要: A preferred embodiment of a symmetric multiprocessor system includes switched fabric (switch matrix) for data transfers that provides multiple concurrent buses enable greatly increased bandwidth between processors and shared memory. high-speed point-to-point Channel couples command initiators memory with the switch matrix I/O subsystems. Each end channel is connected to Interface Block (CIB). The CIB presents logical interface Channel, providing communication path from in another IC. logic similar core-logic transceivers. transport protocol implemented reliably transfer one chip face errors limited buffering.
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