A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

摘要: This paper presents a low-jitter, low-power and small-area injection-locked all-digital PLL (IL-ADPLL). It consists of dual-loop dual-VCO architecture in which one VCO (Replica) is placed TDC-less synthesizable ADFLL to provide continuous tracking voltage temperature variations. The other (main) shares the control with replica but outside loop lower its jitter accurately set frequency desired one. approach avoids timing problems conventional ILPLL since feedback loop. also achieves low power small area, due absence hungry TDC an area-consuming filter, while any PVT IL-ADPLL implemented 65 nm CMOS process measurement results show that it 0.7ps RMS at 1.2 GHz having 1.6 mW 0.97 consumption without intermittent operation resulting FOM -243 dB. consumes area only 0.022 mm2 best performance-area trade-off system presented up-to-date.