System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation

摘要: A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior the case, an interrupt handler pseudo-randomly invalidates number of entries included lookaside buffer (TLB) by changing particular initial interrupts, such as instruction (ISI) or data (DSI). Once processor executes that, turn, triggers interrupt, uses index counter validate invalidate other bits, thus provoking subsequent interrupts. In one embodiment, also changes page table mode that accesses addition TLB.