Identifying stale entries in address translation cache

作者: Manoj Dusanapudi , Vinod Bussa , Shakti Kapoor

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摘要: A mapping may be changed in a table stored memory. The map first set of addresses, for data, to second addresses. changing the including addresses third In response mapping, one or more flush operations executed invalidate entries within address translation caches. include executing operations, test case run. whether any are

参考文章(23)
Varun Mallikarjunan, Satish K. Sadasivam, Prathiba Kumar, Sangram Alapati, Tightly-Coupled Context-Aware Irritator Thread Creation for Verification of Microprocessors ,(2013)
John Te-Jui Sheu, Eric P. Traut, David S. Bailey, Renee Antonio Vega, Method and system for caching address translations from multiple address spaces in virtual machines ,(2005)
Manoj Dusanapudi, Sandip Bag, Sunil Suresh Hatti, Batchu Naga Venkata Satyanarayana, Shakti Kapoor, System and method for testing SLB and TLB cells during processor design verification and validation ,(2007)
Rahul Seth, Shaun M. Conrad, Russell J. Fenger, Gaurav Khanna, Anil Aggarwal, James B. Crossland, Apparatus and Method For Tracking TLB Flushes On A Per Thread Basis ,(2012)