Systematic Studies on Low-Voltage Pentacene Thin-Film Transistors with Low-k Polymer/High-k Oxide Bilayer Gate Dielectric

摘要: We report on the fabrication and characterization of pentacene based thin-film transistors (TFTs) with low-k poly-4-vinylphenol (PVP)/high-k yttrium oxide (YO x ) bilayer gate dielectrics various thickness combinations, for thin-PVP layers (45, 70, 140 nm) thin YO (50 100 nm). Neither nor single layer film alone can properly function as a dielectric due to their very high leakage current. However, our films six different combinations (among which thinnest was PVP/YO = 45/50 nm while thickest 140/100 all exhibited quite good strength ∼2 MV/cm, maximum current standard 10 -6 A/cm 2 . All TFTs successfully demonstrated TFT characteristics at an operating voltage less than -5 V. In particular, two devices studied here (45 PVP 50 thick device performance field effect mobilities (1.74 1.05 cm /V s) on/off ratio ∼10 4 also demonstrate resistance-load inverter below V load resistance (R L 22 MΩ connected nm)/YO (100 layer.