Decomposition and marking of semiconductor device design layout in double patterning lithography

摘要: Provided is a system and method for assessing design layout semiconductor device level determining designating different features of the to be formed by photomasks decomposing layout. The are designated markings that associate various with multiple upon which they will then produced on using double patterning lithography, DPL, techniques. done at included electronic file provided house photomask foundry. In addition overlay critical dimension considerations being decomposed, other criteria, criteria processing their interrelation taken into account, as well environment layers, when marking features.