Method for fabricating a high voltage MOS transistor
作者： Robert W. Busse , Richard A. Blanchard , Richard K. Williams
DOI:
关键词:
摘要: A method is disclosed which produces a high voltage MOS transistor with deep retrograde N-well region, includes buried layer, said well region acting to increase the breakdown of and reduce current gain inherent parasitic bipolar transistor. To achieve degree control over impurity concentration layer without affecting in two dopants species are diffused or implanted N+ layer: one, slow diffusing dopant, such as antimony arsenic, other, more rapidly phosphorus. P- type epitaxial grown an formed layer. Using this method, N arsenic dopant will not out-diffuse into adversely affect between source drain N-well. The out-diffusing phosphorus however, merge diffusion from top form uniform
lens.org 参考文章(12)
E Wajda, H Ghosh, Process for a self-isolation monolithic device and pedestal transistor structure ,(1969)
Roy Nuttall, Clifford Rowbotham, Method of making semi-conductor devices utilizing a compensating prediffusion ,(1973)
Edward G Grochowski, Paul P Castrucci, Thomas L Palfi, William D North, Method of making a common emitter transistor integrated circuit structure ,(1973)
Hideki Yasuoka, Norio Anzai, Method of forming bifets by forming isolation regions connected by diffusion in semiconductor substrate and epitaxial layer ,(1983)
Madhukar B. Vora, Cornel L. Hegedus, Epitaxial outdiffusion technique for integrated bipolar and field effect transistors ,(1972)
Alan Platt, David Dewitt, Harlan R Gates, Isolation in epitaxially grown monolithic devices ,(1968)
David L. Taylor, Method of making junction isolated bipolar device in unisolated IGFET IC ,(1979)
Cornelis Mulder, Arie Slob, Albert Schmitz, Monolithic ic with complementary transistors and plural buried layers ,(1967)