A superconducting sampler for Josephson logic circuits
作者： C. A. Hamilton , F. L. Lloyd , R. L. Peterson , J. R. Andrews
DOI: 10.1063/1.91266
关键词:
摘要: A method is described for automating a technique which used to sample transition duration (rise time) in superconducting logic circuits. The based on measuring the time at biased Josephson junction switches under influence of an applied signal. system limited primarily by jitter estimated be 7 ps. Transition durations as little 9 ps have been observed.
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