Development of the self-aligned titanium silicide process for VLSI applications

摘要: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The produces silicided with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application to NMOS circuits 64K SRAM class 1-µm gate lengths. Comparison circuit yield data test structure parameters from devices fabricated without silicidation demonstrated that is compatible CMOS technologies. some very significant manufacturing advantages over more conventional deposited on In particular, problems associated etching depositing a polycide stack are eliminated since etch replaced much straightforward only etch. As lengths, oxide thicknesses, source-drain junction depths scaled, linewidth control, selectivity underlying oxide, cross-sectional profile control become critical. stringent requirements easily satisfied process.