作者: Ciby Thomas , S Haldar , Rubeena Saleem , R S Gupta
DOI: 10.1080/02564602.1999.11416834
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摘要: A computer aided model to optimize the performance of drain engineered MOS transistors is reported. Simple closed form expressions for cut off frequency, transit time and gate current were derived. comparative study device characteristics made between conventional, spacer LDD Fully Overlapped (FOLD) transistors. Suitable fold finger designs FOLD structures higher lower better driveability. The computed frequency these devices found be in microwave region. structure promises reliability comparison with other structures.