作者: Jing Ye , Yu Hu , Xiaowei Li , Wu-Tung Cheng , Yu Huang
DOI: 10.1109/TVLSI.2013.2256437
关键词:
摘要: Fault diagnosis plays an important role in physical failure analysis and yield learning process. With tens of billions transistors being integrated one chip, multiple faults may exist. faults, fault masking reinforcing effects appear. They cause the conventional single-fault-based methods such as single location at a time (SLAT) to be invalid. The popular SLAT approach fails if there are not enough patterns that can explained by stuck-at fault. Moreover, real silicon defect behave different models (DM) under failing patterns, which invalidate uses single-fault model across all patterns. In this paper, we introduce concept element support models, use fault-element graph (FEG) consider among faults. Based on FEGs most likely locations their elements iteratively identified. Meanwhile, pruned keep track remaining until identified reduced null. Experiments demonstrate proposed method identify even DM with high diagnostic accuracy resolution.