Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults

摘要: In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under (CUT). Generated sets are usually compacted save time which is not good failure diagnosis. Physical defects in circuits modeled by different Fault Models facilitate generation. Stuck-at and transition fault models widely used because of their practicality. this work a Diagnostic Generation (DATPG) system constructed adding new algorithmic capabilities conventional ATPG simulation programs. The DATPG aims generate tests distinguish stuck-at pairs, i.e., two faults must have output responses. This will help diagnosis pin point the narrowing down candidates may be reason particular failure. Given pair, modifying circuit netlist single modeled. Then use target that fault. If generated, it guaranteed pair original circuit. A fast diagnostic algorithm implemented find undistinguished pairs from list given vector set. To determine quality set generated DATPG, proposed Coverage (DC) metric, similar (FC). starts first generating coverage vectors. Those then simulated DC, followed repeated applications generation simulation. We observe improved DC all ISCAS’85 benchmark circuits. between faults, (LOC or LOS type) produces responses faults. By few logic gates one modeling flip-flop under (CUT), extend ability previous