作者: Ashish Kumar Singh , Kareem Ragab , Mario Lok , Constantine Caramanis , Michael Orshansky
DOI: 10.1109/TCAD.2012.2199115
关键词:
摘要: Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting complex behavior scaled transistors to posynomial functions. In this paper, we advance a novel strategy that explicitly handles error model in course optimization. The innovation enabling successive refinement transistor models within gradually reducing ranges operating conditions and dimensions. Refining via brute force requires exponential complexity. key contribution development framework optimizes efficient convex formulations, while SPICE as feasibility oracle identify solutions are feasible with respect accurate rather than fitted model. Due poor fit, standard GP can return grossly infeasible solutions. Our approach dramatically improves feasibility. We accomplish by introducing robust modeling error's sample distribution information To address cases highly stringent constraints, introduce an method identifying true solution through minimal relaxation design targets. demonstrate effectiveness our algorithm on two benchmarks: two-stage CMOS operational amplifier voltage-controlled oscillator designed TSMC 0.18 μm technology. able superior points producing uniformly better power area values under gain constraint improvements up 50% 10% design. Moreover, whereas methods produced violations large 45%, finds