CMOS transistors and methods of forming same
Rajesh Khamankar , Amitabh Jain , Brian Hornung , Nandu Mahalingam
13
2006
Wettability predictions at the oxide ceramic/metal interfaces
P.R. Chidambaram , G.R. Edwards
ASM International, Materials Park, OH (United States)
1996
A 1.2V low leakage low cost 90 nm CMOS wireless technology with a 60 nm transistor gate length
S. Yang , G. Pollack , X. Wang , S. Potla
international symposium on vlsi technology systems and applications 101 -104
2003
Gate length dependent polysilicon depletion effects
Chang-Hoon Choi , P.R. Chidambaram , R. Khamankar , C.F. Machala
IEEE Electron Device Letters 23 ( 4) 224 -226
36
2002
The effect of large oxygen additions on the wettability and work of adhesion of copper-oxygen alloys on polycrystalline alumina
A. Meier , M.D. Baldwin , P.R. Chidambaram , G.R. Edwards
Materials Science and Engineering: A 196 ( 1-2) 111 -117
22
1995
The nature of interfacial phenomena at copper-titanium/alumina and copper-oxygen/alumina interfaces
P.R. Chidambaram , A. Meier , G.R. Edwards
Materials Science and Engineering A-structural Materials Properties Microstructure and Processing 206 ( 2) 249 -258
18
1996
Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed-Mode Simulation Methodology
R. Venugopal , S. Chakravarthi , P.R. Chidambaram
IEEE Electron Device Letters 27 ( 10) 863 -865
15
2006
Modelling of the spreading kinetics of reactive brazing alloys on ceramic substrates: copper–titanium alloys on polycrystalline alumina
A. Meier , P.R. Chidambaram , G.R. Edwards
Acta Materialia 46 ( 12) 4453 -4467
21
1998
Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors
G. Boselli , J. Rodriguez , C. Duvvury , V. Reddy
international electron devices meeting
7
2003
Impact of interconnect technology scaling on SOC design methodologies
N.S. Nagaraj , W.R. Hunter , P.R. Chidambaram , T.Y. Garibay
international interconnect technology conference 71 -73
12
2005
Characterization of high temperature hot dip galvanized coatings
P.R. Chidambaram , V. Rangarajan , W.J. van Ooij
Surface and Coatings Technology 46 ( 3) 245 -253
13
1991
Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS
Chang-Hoon Choi , P.R. Chidambaram , R. Khamankar , C.F. Machala
IEEE Transactions on Electron Devices 49 ( 7) 1227 -1231
23
2002
Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing
P.R. Chidambaram , C. Bowen , S. Chakravarthi , C. Machala
IEEE Transactions on Electron Devices 53 ( 5) 944 -964
239
2006
Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions
S. Chakravarthi , P. Kohli , P.R. Chidambaram , H. Bu
international conference on simulation of semiconductor processes and devices 159 -162
8
2003
Characterization of Zener-tunneling drain leakage current in high-dose halo implants
Chang-Hoon Choi , Shyh-Horng Yang , G. Pollack , S. Ekbote
international conference on simulation of semiconductor processes and devices 133 -136
3
2003
A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer
B. Hornung , M. Bevan , P. Nicollian , P.R. Chidambaram
symposium on vlsi technology 85 -86
4
2003
90 nm CMOS RF technology with 9.0 V I/O capability for single-chip radio
G. Baldwin , J. Ai , K. Benaissa , F. Chen
symposium on vlsi technology 87 -88
12
2003
35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS
P.R. Chidambaram , B.A. Smith , L.H. Hall , H. Bu
symposium on vlsi technology 48 -49
101
2004
An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes
R. Khamankar , H. Bu , C. Bowen , S. Chakravarthi
symposium on vlsi technology 162 -163
19
2004
10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling
Sam Yang , Yanxiang Liu , Ming Cai , Jerry Bao
symposium on vlsi technology
7
2017