NAND flash memory technology utilizing fringing electric field
作者： Jong-Ho Lee , Sang-Goo Jung
DOI: 10.1016/J.MICROREL.2011.09.029
关键词: Flash memory 、 Nanowire 、 Communication channel 、 Engineering 、 Electric field 、 Scalability 、 C++ string handling 、 Charge trap flash 、 Electrical engineering 、 Node (physics)
摘要: Abstract In this review article, basic properties of NAND flash memory cell strings which consist cells with virtual source/drain (S/D) (or without S/D) were discussed. The S/D concept has advantages better scalability, less fluctuation due to effectively longer channel length at the same technology node, and program disturbance. fringing electric field from control-gate and/or floating-gate is essential induce (charges) in space region body between control-gates becomes effective as size shrinks. A string consisting planar silicon-oxide-nitride-oxide-silicon (SONOS) formed bulk Si substrate needs have a bit-line doping ∼5 × 1017 cm−3 keep high read current. floating gate (FG) gives larger current compared that SONOS given similar doping. Non-planar like arch fin-type structures more focus on region. also useful 3-dimensional (3-D) stacked where thin film nanowire, nanotube) adopted.
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