Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms
作者： Muhsen Owaida , Hantian Zhang , Ce Zhang , Gustavo Alonso
DOI: 10.23919/FPL.2017.8056784
关键词: Decision tree 、 K-D-B-tree 、 Parallel computing 、 Speedup 、 Fractal tree index 、 Incremental decision tree 、 Scalability 、 Computer science 、 Central processing unit 、 ID3 algorithm
摘要: Decision tree ensembles are commonly used in a wide range of applications and becoming the de facto algorithm for decision based classifiers. Different trees an ensemble can be processed parallel during inference, making them suitable use case FPGAs. Large ensembles, however, require careful mapping to on-chip memory management accesses. As result, existing FPGA solutions suffer from inability scale beyond tens lack flexibility support different ensembles. In this paper we present classifier together with software driver efficiently manage FPGA's resources. The architecture utilizes resources fit half million nodes memory, delivering up 20× speedup over 10-threaded CPU implementation when fully processing on FPGA. It also combine that do not achieving order magnitude compared pure implementation. addition, programmed at runtime process varying sizes.
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