Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices

摘要: Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such require each non-volatile (NVM) element have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage all other cells. Using circuit-level SPICE simulations, we explore design constraints on composed of generic NVM (+1R) together with the AD developed by our group, based Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is most stringent constraint for large 1AD+1R arrays. As array size grows, in order keep write power-efficient, voltage at “turns on” outpace switching voltage. Failure achieve this condition causes total power, injected into ensure success worst-case single-bit greatly exceed actual power. Extensive tolerancing results current parameters (subthreshold slope series resistance) are also important, but same degree as characteristics. scaled MIEC devices (Voltage Margin $V_{m} \sim $ 1.54V) can support 1 Mb voltages up 1.2V, stacking two could enable $\sim 2.4\text{V}$ . The impact $V_{m}$ variability quantified—we there minimal degradation margin variabilities (standard deviation ) very different from those already demonstrated experimentally.