Non-volatile memory having 3d array architecture with bit line voltage control and methods thereof
作者： Raul Adrian Cernea
DOI:
关键词: Voltage regulator 、 Voltage 、 Node (circuits) 、 Load line 、 Electronic engineering 、 Voltage reference 、 Comparator 、 Non-return-to-zero 、 Line driver 、 Engineering
摘要: In a 3D memory with vertical local bit lines, each line is switchably connected to node on global having first and second ends, the voltage maintained at predetermined reference level in spite of being driven by driver from end that constitutes variable circuit path length serial resistance. This accomplished feedback regulator comprising clamp controlled comparator line. The compares sensed outputs control this way regulated voltage.
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