Vertical transistor with hardening implatation
作者： Young Pil Kim , Maroun Georges Khoury , Peter Nicholas Manos , Hyung-Kew Lee , Dadi Setiadi
DOI:
关键词:
摘要: A method includes providing a semiconductor wafer having plurality of pillar structures extending orthogonally from the wafer. Each structure forms vertical transistor top surface and side orthogonal to surface. Then hardening species is implanted into oxidized form oxide layer. The layer removed rounded surfaces.
lens.org 参考文章(34)
John W. Robinson, Grzegorz Kaganowicz, John H. Thomas, Low temperature growth of silicon dioxide on silicon ,(1984)
Sang-Yun Lee, Method for making a three-dimensional integrated circuit structure ,(2004)
Gurtej Singh Sandhu, Randhir P. S. Thakur, Method for fabricating stacked layer silicon nitride for low leakage and high capacitance ,(1994)
Antoine Khoueir, YoungPil Kim, Hsing-Kuen Liou, Maroun Khoury, Yongchul Ahn, Hyung-Kyu Lee, Peter Nicholas Manos, Paramasiyan Kamatchi Subramanian, Dadi Setiadi, Jinyoung Kim, Chulmin Jung, Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements ,(2009)
Sang-Yun Lee, Semiconductor Layer Structure And Method Of Making The Same ,(2008)
Sang-Yun Lee, Electronic circuit with embedded memory ,(2005)
Hirokazu Kurisu, Kazuaki Ohmi, Kiyofumi Sakaguchi, Kazutaka Yanagita, Composite member and separating method therefor, bonded substrate stack and separating method therefor, transfer method for transfer layer, and SOI substrate manufacturing method ,(2000)
Sang-Yun Lee, Three-dimensional integrated circuit structure ,(2006)
Michael Belyansky, Andreas Knorr, Oleg Glushenkov, High density plasma oxidation ,(2003)
William C. Herben, Rogerio H. Silva, Coy M. Fielder, Gary D. Wells, Expandable eccentric reamer and method of use in drilling ,(2004)