Configuration bus interface circuit for FPGAs
作者： David P. Schultz , Lawrence C. Hung , F. Erich Goetting
DOI:
关键词: Field-programmable gate array 、 Bitstream 、 Multiplexer 、 Electronic engineering 、 Interface (computing) 、 Network packet 、 Programmable logic device 、 Electronic circuit 、 Computer science 、 Computer hardware 、 State (computer science)
摘要: A bus interface circuit for a programmable logic device (PLD) including an multiplexer connected between two or more external communication circuits and configuration memory array. The coordinates selected one of the packet processor. processor interprets command/data information transmitted in bit stream from circuit. In default state, connects dual-purpose input/output pins PLD to alternative JTAG facilitate operations through PLD.
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