Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

作者: H.-H. Vuong , C.S. Rafferty , S.A. Eshraghi , J.L. Lentz , P.M. Zeitzoff

DOI: 10.1109/16.502426

关键词: Electronic engineeringShort-channel effectPMOS logicDopantThreshold voltageDrain-induced barrier loweringOptoelectronicsTransient (oscillation)DopingMaterials scienceDiffusion (business)

摘要: We present a model which simulates the trapping of arsenic and boron dopants at silicon-silicon dioxide interface, demonstrate that this gives significantly more accurate doping profiles for wide range PMOS devices, as characterized by device Threshold Voltage. In addition, newly-developed Transient Enhanced Diffusion (TED) is applied first time to process simulation buried-channel predicting an enhanced Short Channel Effect Drain Induced Barrier Lowering (DIBL) effect. By using both these models, excellent agreement achieved between simulated measured characteristics devices with gate lengths varying from 2 0.4 /spl mu/m, over bias conditions operating temperatures.

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