Method and apparatus for interconnect-driven optimization of integrated circuit design

摘要: A method and an apparatus are provided for post-layout optimization of integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement routing provided, so as avoid the costly design iteration loop that requires re-synthesis, re-place re-route. Optimization can be in multiple phases each accomplishing a specified set transformations. Static timing analysis is performed at end determine if further steps required. physical first scanned mismatch between drivers loads. Then, second phase, “hot spots” identified transformation using “bidirectional combinational total negative slack” (BCTNS) algorithm. subsequent phases, based on meeting setup times hold critical path performed.