Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units
作者： Mauro Olivieri , Francesco Pappalardo , Simone Smorfa , Giuseppe Visalli
DOI: 10.1109/TCSII.2007.896937
关键词: Algorithm 、 Error detection and correction 、 Word error rate 、 Reduction (complexity) 、 Computer science 、 Power (physics) 、 Limit (mathematics) 、 Image processing 、 System on a chip 、 Floating point
摘要: Leading zero anticipation with error correction is a widely adopted technique in the implementation of high-speed IEEE-754-compliant floating-point units (FPUs), which are critical for area and power multimedia-oriented systems-on-chips. We investigated novel LZA algorithm allowing us to remove circuitry by reducing rate below commonly accepted limit image processing applications, not achieved previous techniques. embedded our into complete FPU definitely obtaining both saving overall latency reduction respect traditional designs.
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