High-Speed Error-Correction for Leading Zero/One Anticipator
作者： Ling-hao Li , Zhi-biao Shao , Li Wang
DOI: 10.1109/CISE.2010.5677177
关键词:
摘要: The algorithm and its implementation of a leading zero anticipators (LZA) are very vital for the performance high-speed floating-point adder in current state art microprocessor design. However, predicting "shift amount" by conventional LZA design, there may be one-bit error, which is mentioned as possible error result. This paper compares designs presents novel parallel error-detection modifying result before it sent off to improve LZA. does not depend on any carry-in signals adder. Therefore, makes error-correction with mantissas addition increases speed generate correct results significantly.
sci-hub.se 参考文章(9)
L.V. Tran, W.P. Hayes, R.N. Kershaw, L.E. Bays, J.R. Boddie, E.M. Fields, R.L. Freyman, C.J. Garen, J. Hartung, J.J. Klinikowski, C.R. Miller, K. Mondal, H.S. Moscovitz, Y. Rotblum, W.A. Stocker, J. Tow, A 32-bit VLSI digital signal processor IEEE Journal of Solid-state Circuits. ,vol. 20, pp. 998- 1004 ,(1985) , 10.1109/JSSC.1985.1052427
Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli, Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 54, pp. 685- 689 ,(2007) , 10.1109/TCSII.2007.896937
Ge Zhang, Wei-Wu Hu, Zi-Chu Qi, Parallel error detection for leading zero anticipation Journal of Computer Science and Technology. ,vol. 21, pp. 901- 906 ,(2006) , 10.1007/S11390-006-0901-3
T. Lang, J.D. Bruguera, Floating-point multiply-add-fused with reduced latency IEEE Transactions on Computers. ,vol. 53, pp. 988- 1003 ,(2004) , 10.1109/TC.2004.44
H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, T. Sumi, Leading-zero anticipatory logic for high-speed floating point addition IEEE Journal of Solid-state Circuits. ,vol. 31, pp. 1157- 1164 ,(1996) , 10.1109/4.508263
Giorgos Dimitrakopoulos, Kostas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos, None, Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units IEEE Transactions on Very Large Scale Integration Systems. ,vol. 16, pp. 837- 850 ,(2008) , 10.1109/TVLSI.2008.2000458
Robert D. Maher, Circuit for simultaneous arithmetic calculation and normalization estimation ,(1989)
M.S. Schmookler, K.J. Nowka, Leading zero anticipation and detection-a comparison of methods symposium on computer arithmetic. pp. 7- 12 ,(2001) , 10.1109/ARITH.2001.930098
David Galbi, Hon P. Sit, Alfred K. Chan, Prenormalization for a floating-point adder ,(1989)