The Calculation and Anticipation Unit for Floating-Point Addition

摘要: Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new unit called the calculation and anticipation (C&A) is presented for IEEE 754 standard floating-point adder (FPA) that most important frequently used part both modern CPUs GPUs. C&A parallelize rounding step readjustment step, which are known as time-consuming steps addition with significand addition. Therefore it reduces FPA critical path delay enormously, even more decreases little area occupation. The synthesis results show double-precision takes about 17.17% improvement in delay, while saves 8.32% than conventional one. It 5.90% advantage 19.58% worst case from Open Core module "fpu_double" (rev 14 2010-02-13) synthesized same 0.13-μm CMOS bulk. Furthermore, comparing two-path using LSI Logic's gflxp 0.11-μm library, 4.30% almost one-third number of individual cells.