摘要: Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower additions. A double implemented with the improved single-path algorithm is modified design a supports both single similar technique used quadruple implements two-path algorithm. The To estimate area worst-case delay, double, quadruple, adders are in VHDL using algorithms. correctness of all designs tested verified through extensive simulation. Synthesis results show designed require roughly 26% more 10% delay than same obtained for requires 33% 35% 13% 18% adders, respectively.
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