作者: JK Lan , YL Wang , YL Wu , HC Liou , JK Wang
DOI: 10.1016/S0040-6090(00)01289-X
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摘要: Abstract The electrical performance of hydrogen silsesquioxane (HSQ) as the interlayer level dielectric (ILD) has been determined by using two-metal-layered test structures to study impact oxide liner thickness on capacitance reduction. In comparison with SiO 2 , HSQ formed cap and or only, have 20–27% lower intraline while 6–16% reduction was observed for fluorosilicate glass (FSG) relative . It found that /HSQ ILDs did not vary expected. Similar effects were via resistance measurement. Analysis structure shows wide variation /HSQ/SiO stack after Chemical Mechanical Polishing (CMP) step changed expected contribution capacitance. This also a strong landed/unlanded resistance. Therefore, good control CMP ILD is needed reduce liner/HSQ/cap which in turn will enhance process yields 0.18 μm devices.